Generally speaking, Tunnel Field Effect Transistors (TFET) are increasingly envisaged for replacing CMOS type transistors, particularly for low power applications. Tunnel effect (also known as tunnel junction) transistors are gate PiN diodes where the current in the on state comes from carriers passing from band to band by tunnel effect. TFET have in fact very low leakage currents Ioff (current in the off state of the transistor) as well as low subthreshold slopes (SS) compared to CMOS transistors of similar dimension. An example of structure of a double gate N type TFET 1 is illustrated in FIG. 1. The TFET 1 is based on a PiN diode architecture with one gate and comprises:                a p+ doped source semiconductive area 2;        an intrinsic central channel semiconductive area 3;        an n+ doped drain semiconductive area 4;        two gate areas 5 and 6, for example metallic, above and below the intrinsic area 3 and separated therefrom by a gate dielectric layer (respectively 7 and 8).        
The dielectric material of the gate dielectric layer is usually a material with high dielectric constant, referred to as “high-k” material; such a material makes it possible in particular to obtain better conduction currents.
On either side of the source area 2 there are source conductive areas 9 and 10 (for example made of NiSi) formed for example by silicidation.
Similarly, on either side of the drain area 4 there are drain conductive areas 11 and 12 (for example made of NiSi) formed for example by silicidation.
The source conductive areas 9 and 10 are respectively isolated from the gate areas 5 and 6 (and their associated dielectric layer) by spacers 13 and 14.
The drain conductive areas 11 and 12 are respectively isolated from the gate areas 5 and 6 (and their associated dielectric layer) by spacers 15 and 16.
FIG. 2 illustrates the band diagrams of the device 1 as a function of the position along the device 1 and according to the voltages applied to the gate, to the drain and to the source.
The operating principle is the following: by applying a positive voltage at the level of the drain (here VD=1V), the PiN diode is reverse biased thereby creating a potential barrier such that a very low current Ioff is obtained in off mode. By applying a positive gate voltage (here VG=1.6V), the probability of tunnel transition on the source side is increased by bringing together the valence and conduction bands. The transport is then assured by the source/drain electrical field.
As mentioned above, one of the advantages of the TFET is that it offers a very low leakage current Ioff compared to a CMOS transistor (and thus a reduced dissipated power in off mode).
One of the problems of TFET resides nevertheless in their dynamic operating performance. Two reasons explain the relatively poor dynamic operating performances.
Firstly, TFET have a weak conduction current intensity Ion (i.e. current in the on state of the transistor) compared to the values of Ion obtained for CMOS transistors of similar dimension.
Moreover, TFET have high parasitic capacitances, particularly the gate-drain capacitance also known as Miller capacitance: in increasing, these parasitic capacitances reduce the dynamic operating frequency.